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In addition, IRQCFG0E allows several internal interrupts to be configured. See Table 79 below:
IRQCFG0E bits
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
Cfg
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
Internal Interrupt Control
Start FIFO fill when start pattern detected
Control FIFO with bit 6
Stop filling FIFO (if bit 7 is 0, this is start pattern detect)
Start filling FIFO
Transmitting all pending bits in FIFO
All bits in FIFO transmitted
FIFO OK
FIFO overflow (write 1 to reset FIFO)
Disable RSSI interrupt (bit 2)
Enable RSSI interrupt (bit 2)
RF signal ≥ RSSI threshold
RF signal < RSSI Threshold
PLL not locked
PLL locked
PLL_LOCK signal disabled (bit 1 above), Pin 23 set high
PLL_LOCK signal enabled
Table 79
MCFG0C bits 7..6 set the length of the FIFO as shown in Table 80:
MCFG0C bits 7..6
00
01
10
11
FIFO Length
16 bytes
32 bytes
48 bytes
64 bytes
Table 80
The integer value of MCFG0C bits 5..0 plus 1 sets the FIFO interrupt threshold. When receiving in Buffered data
mode, FIFO_Int_Rx is triggered when the number of bytes in the FIFO is equal to or greater than the threshold.
The FIFO threshold facilitates sending and receiving messages longer than the chosen FIFO length, by signaling
when additional bytes should be added to the FIFO during a packet transmission and retrieved from the FIFO dur-
ing a packet reception. Two additional interrupts, nFIFOEMPY and FIFOFULL provide signaling that a packet
transmission is complete or a full packet has been received respectively.
The following is a typical Buffered data mode operating scenario. There are many other ways to configure this
very flexible data mode.
1. Switch to standby mode by setting MCFG00 bits 7..5 to 001.
2. Set the FIFO to a suitable size for the application in MCFG0C bits 7..6.
3. Set the start pattern length in RXCFG12 bits 4..3.
4. Load the start pattern in registers SYNCFG16 up through SYNCFG19 as required.
5. Set IRQCFG0E bit 7 to 0. In receive, the FIFO will start filling when a start pattern is detected.
6. Set IRQCFG0D bit 7..6 to 01. In receive, IRQ0 will flag each time a byte is ready to be retrieved.
7. Set IRQCFG0D bit 5..4 to 00. IRQ1 signaling will not be required in receive mode.
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TRC105 - 05/29/13
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